Design/Manufacturing Parameters |
Standard Technology |
Advanced Technology |
Future Technology |
Minimum Internal Line Width |
0.005″ |
0.003″ |
>0.002″ |
Minimum Internal Spacing |
0.005″ |
0.002″ |
>0.002″ |
Minimum External Line |
0.005″ |
0.003″ |
>0.002″ |
Minimum External Spacing |
0.005″ |
0.002″ |
>0.002″ |
Minimum Internal Copper Foil |
0.0007″ |
0.00035″ |
0.000175″ |
Maximum Internal Copper Foil |
0.0042″ |
0.0056″(+) |
0.0084″(+) |
Minimum External Copper (TOTAL) |
0.0014″ |
0.0007″ |
0.00035″ |
Maximum External Copper (TOTAL) |
0.0084″ |
0.0112″ |
0.0168 |
Minimum Internal Pad Over Drilled Hole Size |
0.012″ |
0.006″ |
0.004″ |
Minimum External Pad Over Drilled Hole Size |
0.010″ |
0.006″ |
0.004″ |
Minimum Drilled Hole Size |
0.010″ |
0.006″ |
>0.005″ |
Minimum Aspect Ratio |
12:01 |
16:01 |
18:01 |
Minimum Finished Hole Tolerance |
0.003”+/- |
0.002”+/- |
0.001”+/- |
Minimum SMT Pitch |
0.015” |
0.010” |
>0.0012” |
Maximum Layer Count |
22 Lyr |
30+ Lyr |
50+ Lyr |
Minimum Dielectric Thickness |
0.002” |
0.0012” |
>0.0012” |
Maximum Overall Thickness |
.250 |
.400” |
.750” |
Minimum Board Thickness (Multi-Layer) |
.031” |
.014” |
.008” |
Buried Resistor Tolerance |
|
30% |
15% |
Buried Capacitance PF / in 2 |
|
500 |
600 |